Broadway SPR Rules + Notes + Mini Guides + Misc Random Stuff

I have made this document when I needed a quick reference card to messing around with Broadways' special purpose registers. Might as well share it for anyone who needs it.

Utilizing the Condition Register

For Advanced ASM Coders

• Understand the basics of using compare and branch instructions
  
• Understand binary/bits + Logical Operations
  

• bit 0 = Less-Than flag (LT)
  
• bit 1 = Greater-Than flag (GT)
  
• bit 2 = Equal flag (EQ)
  
• bit 3 = Summary Overflow flag (SO)
  

• Condition Register Logical OR~
  cror crfD, crfA, crfB #crfA bit is logically OR'd with crfB bit. Result is written to crfD bit.
  
• Condition Register Logical AND~
  crand crfD, crfA, crfD #crfA bit is logically AND'd with crfB bit. Result is written to crfD bit.
  
• Condition Register Logical NOR~
  crnor crfD, crfA, crfD #crfA bit is logically NOR'd with crfB bit. Result is written to crfD bit.
  
• Condition Register Logical XOR~
  crxor crfD, crfA, crfD #crfA bit is logically XOR'd with crfB bit. Result is written to crfD bit.
  
• Condition Register Logical EQV (XNOR)~
  creqv crfD, crfA, crfD #crfA bit is logically XNOR'd with crfB bit. Result is written to crfD bit. Technically, the instruction does a XOR of crfA with crfD, then this temp result is complemented, then writes that result to crfD.
  
• Condition Register Logical AND with Complement~
  crandc crfD, crfA, crfD #crfA bit is logically AND'd with the complemented crfB bit. Result is written to crfD bit.
  
• Condition Register Logical OR with Complement~
  crorc crfD, crfA, crfD #crfA bit is logically OR'd with the complemented crfB bit. Result is written to crfD bit.
  

• Setting a bit high (set cr0 EQ high)~
  crset 4*cr0+eq #creqv 4*cr0+eq, 4*cr0+eq, 4*cr0+eq; crF bit is XNOR'd with itself and resutl written to same bit spot
  
• Setting a bit low (set cr0 EQ low)~
  crclr 4*cr0+eq #crxor 4*cr0+eq, 4*cr0+eq, 4*cr0+eq; crF bit is XOR'd with itself and result written to same bit spot
  
• Copy-Pasting (Moving) a bit (copy cr0 EQ bit to cr7 EQ bit's spot)
  crmove 4*cr7+eq, 4*cr0+eq #cror 4*cr7+eq, 4*cr0+eq, 4*cr0+eq; crF bit is Or'd with itself and result writen to crfD
  
• Flip a bit (flip cr0 EQ bit and place result in cr7 EQ bit's spot))
  crnot 4*cr7+eq, 4*cr0+eq  #crnor 4*cr0+eq, 4*cr0+eq, 4*cr0+eq; crF bit is NOR'd with itself and result written to crfD
  

• mfcr rD #Contents of the CR is copied to rD
  
• mtcr rD #Contents of rD is copied to the CR
  
• mcrf crD, crA #Condition Field A is copied to Condition Field D
  

All About Cache

This PowerPC tutorial will teach you the in's and out's of the Cache model of the Wii Broadway Chip, it's instruction set, and how some of these instructions may need to be used for Gecko ASM Codes. This is a lengthy read, but every PPC Coder/dev should have a decent understanding of Broadway's Cache model.

• Virtual Cached Memory
  
• Virtual Uncached Memory
  

• 0x00000000 thru 0x017FFFFF Physical Mem1
  
• 0x10000000 thru 0x13FFFFFF Physical Mem2
  
• 0x80000000 thru 0x817FFFFF Virtual Cached Mem1 (known as mem80 and mem81)
  
• 0x90000000 thru 0x93FFFFFF Virtual Cached Mem2 (known as mem9)
  
• 0xC0000000 thru 0xC17FFFFF Virtual Uncached Mem1
  
• 0xD0000000 thru 0xD3FFFFFF Virtual Uncached Mem2
  

• Data Cache
  
• Instruction Cache
  

• M = Modified
  
• E = Exclusive
  
• I = Invalid
  

• V = Valid
  
• I = Invalid
  

• dcbf For cache hits, if the block has a M bit, the data in the block is now written to physical memory and an I bit replaces the M bit. If the block has an E bit, the bit is simply changed to I. For cache misses, no action is taken. Therefore you can use dcbf as a way to "erase" the Cache but make sure memory gets updated before Cache is erased. For "erasing" Cache without updating memory, refer to dcbi.
  
• dcbst For cache hits, if the block has an E bit or I bit, no action is taken. If the block has a M bit, the data in the block is written to physical memory and the bit is changed to E. For cache misses, no action is taken. Pro-Tip: If you are familiar with BAT Registers and the region of memory is in a BAT that is marked at 'Write-Through (W bit high), you will never need the dcbst instruction for that region of memory, but performance of Broadway will be degraded.
  
• dcbi For cache hits, the state bit is always changed to I, regardless of what is was before. If the state bit was M, data that was going to be written to physical memory is now discarded. For cache misses, no action is taken. Therefore, dcbi can be used to "erase" the Cache and prevent the Cache from updating physical memory.
  
• dcbt This is used to give the Cache system a hint that an upcoming Load instruction needs to have its 32-bit aligned Address pushed onto the cache. Thus, this is only useful if you know the Load instruction will end up as a Cache Miss. For cache hits, no action is taken. Improper usage of this instruction (too many Cache hits) will degrade performance.
  
• dcbtst This is used to give the Cache system a hint that an upcoming Store instruction needs to have its 32-bit aligned Address pushed onto the cache. Thus, this is only useful if you know the Store instruction will end up as a Cache Miss. For cache hits, no action is taken. Improper usage of this instruction (too many Cache hits) will degrade performance.
  
• dcbz For cache hits, the contents of the Block (virtual memory) are zero'd, and state bit changed to M. For cache misses, a new block using the address referenced by the dcbz is pushed onto the Cache, then the Cache Block is zero'd (regardless of what is present in Physical Memory) & tagged with the M bit. 
  
• dcbz_l does the same as above, but will then lock the cache where it can't be modified. This instruction is only legal when the Locked Cache (via HID2) is enabled, otherwise an exception will occur.
  
• icbi is the only instruction you have available to modify the instruction cache. For cache hits, the block is set to Invalid. For cache misses, no action is taken.
  

• dcbst 0, rX = This will force the block (if M bit tagged) to be written to physical memory. State bit changed to E.
  
• icbi 0, rX = The old instruction may still be present (and marked Valid) in the Instruction Cache. Therefore, we tag it as Invalid
  
• isync = Broadway is an out-of-order execution CPU like any other modern CPU. Even with the icbi instruction, it's possible Broadway still fetched the older instruction. This isync instruction will force Broadway to purge its current fetched instructions and refetch. Thus forcing the new instruction to be fetched.
  

• Write-Back = store operations update the cached memory, but do not instantly update physical memory
  
• Write-Through = store operations update cached memory, plus updating physical memory. performance is degraded.
  

• L1 Instruction Cache
  
• L2 Instruction Cache
  
• Physical Memory (may also be called System or Main memory in various manuals/websites)
  

• Waits for all prior instructions to complete
  
• Prevents future instructions from completing until isync itself completes
  
• Future instructions that were already fetched, are purged then refetched
  

• Waits for all prior instructions to complete
  
• Waits for all Memory Accesses caused by prior instructions to complete
  
• Prevents future instructions from completing until Sync itself completes
  

• Some external (non-PowerPC) device (i.e. Starlet, DSP engine, DMA engine, EEPROM chip) is accessing Memory (the 32-byte block in question) in any way.
  
• Another PowerPC core or processor is accessing Memory (the 32-byte block in question) in any way
  
• TLB invalidations (from the core that is executing the self modifying code itself, *NOT* some other core)
  
• Page Table R and C bits being accessed by other cores, processors, or external devices
  

• Page Tables are being utilized (which thus uses TLBs)
  
• There is another core within Broadway or another Broadway processor present (which is impossible since Broadway is single core uni-processor), and cache coherency between all cores and/or processors must be maintained
  
• Some external device (i.e. Starlet) is accessing the memory utilized by the self-modifying code
  

Hey. 

I need some help with creating a code that lets you drag any item, just like the draggable blueshell mod (https://mariokartwii.com/showthread.php?...=draggable)

For example to drag a star i've tried the following:

1) Item Behaviour Modifier, https://mariokartwii.com/showthread.php?tid=386) but it also activates the power before dragging it.
048A61B8 00000002

2) I changed this code to the following (taken the PAL code for star from Item Behaviour Modifier):

068A61B8 00000008
00000002 00000000. 
This does not activate the power up when pressing the item button (nice!), and the item actually drags behind the vehicle. However, when pressing the button again, it drops the item on the ground (like a banana)


I want to drag things like POW, Shocks, Bloopers, Megas in order to simulate a mario kart 8 Deluxe where you have 2 item slots.

Is this even possible as these items have a standard behaviour value of 00 instead of 01, like the blueshell/red shell/green shell (https://wiki.tockdom.com/wiki/Filesystem...r_Modifier)

Kind regards,
Dirtyfrikandel

Hey,

Does anyone have either of the following software:

• Bean's auto porter
  
• Bully@WiiPlaza's Gecko Code Porter
  

is it possible to change a text box message id at runtime? for example:
Luigi Circuit - ID 320 for example
and i want it to change to
Another circuit - ID 321

EVA Usage List

Some codes use the area adjacent of the Exception Vectors. This area is commonly referred to as simply the 'EVA'. It is segments of unused regions of memory that are universal for every Wii game. Some code creators will utilize these regions of memory to transfer data between multiple codes.

Therefore, care must be taken so two different codes don't end up using the same spot(s) in the EVA. Further below is a list of codes that use the EVA along with their used EVA addresses.

You will notice that there are some instances where multiple codes use the same EVA addresses. Regarding MKWii, there are other unused regions of memory that are used by codes as well (i.e. mem81). If such codes use those space(s), they are also included.

Some codes are listed more than once because they use 2 or more different regions of the EVA/Mem81/etc. There's a good chance I missed some codes that need to be on the list. Please let me know if you find any missing codes, missing EVA usage of code(s), or other mistakes. Thank you.

boks 267 - YouTube

Hi I'm Zi/StereoCat/Rosuku/Roskzy/Rosk/Sazry/Sazry666 I go by a few names
I'm bored and I feel like coming back to the mkwii community again but I'm not as active at all.
YT: ASL
Wiki: 267

After playing some battles online, I realized that players don't receive points until a few seconds after they hit their opponent. This is problematic because during the last 2-3 seconds of the battle, nobody can earn any points. I was thinking of a way this could possibly be fixed, it happens way too often when I'm battling online.

My idea is: a code that allows players to earn/lose points for 2 more seconds after time runs out.

If anyone can make this code, I would really appreciate it.