Lol, look at this source, Does anybody wanna optimize it?
#1
This is for a better color transition in my most recent code that I co-created w/ Sponge, the Mii Head rainbow color cycler.

I was able to achieve Max Color 'Fluidity' with the source below, but it is very unoptimized. The code (C0 type) WORKS btw. I was under the impression that Xor, Xori, and Xoris had RC options, but they don't. So ofc, there's something I'm doing that is not correct for optimization.

The rainbow color spectrum startsand ends at Red. Sorry for lack of notes.

Code:
lis r12, 0x8000
lwz r11, 0x0998 (r12)
srwi r11, r11, 8

lbz r10, 0x099C (r12)

cmpwi r11, 0
bne- skip_initial_setup

lis r11, 0x00FF
li r10, 0

skip_initial_setup:
cmpwi r10, 0
beq- increase_2nd_byte
cmpwi r10, 1
beq- decrease_1st_byte
cmpwi r10, 2
beq- increase_3rd_byte
cmpwi r10, 3
beq- decrease_2nd_byte
cmpwi r10, 4
beq- increase_1st_byte

#decrease_3rd_byte
subi r11, r11, 0x0001
xoris r0, r11, 0x00FF
cmpwi r0, 0
bne- update_then_shift_back

li r10, 0

b update_then_shift_back

increase_2nd_byte:
addi r11, r11, 0x0100
lis r0, 0x00FF
ori r0, r0, 0xFF00
xor r0, r11, r0
cmpwi r0, 0
bne- update_then_shift_back

li r10, 1

b update_then_shift_back

decrease_1st_byte:
subis r11, r11, 0x0001
xori r0, r11, 0xFF00
cmpwi r0, 0
bne- update_then_shift_back

li r10, 2

b update_then_shift_back

increase_3rd_byte:
addi r11, r11, 0x0001
xori r0, r11, 0xFFFF
cmpwi r0, 0
bne- update_then_shift_back

li r10, 3

b update_then_shift_back

decrease_2nd_byte:
subi r11, r11, 0x0100
xori r0, r11, 0x00FF
cmpwi r0, 0
bne- update_then_shift_back

li r10, 4

b update_then_shift_back

increase_1st_byte:
addis r11, r11, 0x0001
lis r0, 0x00FF
ori r0, r0, 0x00FF
xor r0, r11, r0
cmpwi r0, 0
bne- update_then_shift_back

li r10, 5

update_then_shift_back:
slwi r11, r11, 8
ori r11, r11, 0x00FF

stw r11, 0x0998 (r12)
stb r10, 0x099C (r12)

#Find Region of Game

lbz r0, 0x5F27 (r12) #Instruction here is vital. Virtually impossible for this to be modded by something unrelated

lis r9, 0x8024 #All Mii Head Addr's start with this upper 16 bits

cmpwi r0, 0xEC #pal
ori r12, r9, 0xB8B0
beq- set_ctr

cmpwi r0, 0x10 #japan
ori r12, r9, 0xB260
beq- set_ctr

cmpwi r0, 0x54 #korea
ori r12, r9, 0xB688
beq- set_ctr

#usa
ori r12, r9, 0xB598

#Loop Stuff, Write Color

set_ctr:
li r0, 40 #40 (0x28) total consecutive words at memory to be rewritten
mtctr r0

loop:
stw r11, 0 (r12)

dcbst 0, r12 #These 4 instructions for clearing cache, its most likely needed. Too lazy to test w/o, lul.
sync
icbi 0, r12
isync

addi r12, r12, 4
bdnz+ loop
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Lol, look at this source, Does anybody wanna optimize it? - by Vega - 01-27-2020, 08:50 PM

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