First, my bad on the xnor instruction. It's known as eqv in Broadway (.i.e. eqv rD, rA, rB)
1.
With Update: Updates the Source Address with new value based on VALUE
Algebraic: I've never once used algebraic labeled instructions believe it or not.
Here's the definition of Load Half Word Algebraic btw (there's other algebraic instructions ofc such as sraw)
The halfword at the Effective Address is loaded in the lower 16 bits of rD. The remaining bits in rD are filled with a copy of the most significant bit of the loaded halfword.
So if the halfword loaded of 0x8000, it will actually load as 0xFFFF8000. Cause the first bit in 0x8000 is 1. Fill every bit of 1 in the upper 16 bits is 0xFFFF.
Negative halfwords in memory take up 32-bits of space (i.e. 0xFFFFFFFD = -3). So what compilers can do to save space in memory is store negative halfwords via sth, so the lower 16 bits are stored to memory only, then the compilers can load these values later with lha to sign-extend them in the register. Example: store the halfword of 0xFFFF8000, will only store 0x8000 to memory, now load it with lha so it loads as 0xFFFF8000. Btw 0xFFFF8000 is -32768 and is the 'lowest' negative number for the 16-bit signed range
Indexed: No use of VALUE, instead another Source Register is used for the Effective Address calculation
2.
Some I know right off the bat...
addi, addis, subi, subis, addic., subic.
Every store/load instruction that is NOT lwm,stwm,lswi,stswi (i havent ever checked lswx, stswx btw). Actually I've never checked the other ones, a generic PowerPC manual I read ages ago claimed that. Btw the Broadway manual (from what ive seen) doesnt have a quick reference/list about instructions and literal 0. There is probably a small paragraph buried somewhere in the manual about it. You could go thru the pain of testing up a bunch of mock instructions with non-zero values in their source registers, and log the results.
3. A quick glance on the file shows its for PowerPC 405. Broadway is based off of PowerPC 750.
4. Its just for example. The point I was making is that the Source Register gets updated with a new value.
5. Whoever told you that is wrong. Compile a not r5, r3 instruction and a nor r5, r3, r3 instruction. It will compile as the same 32-bit code. Go on Dolphin, pause emulation, place in the value of 1 in r3. Execute a not r5, r3 instruction. r5 will equal -2 instead of -1. That's because every bit in a not instruction gets flipped.
Now redo this same example but use neg r5, r3. And r5 will then equal -1, which is obviously the negative value of positive 1.
6. Ye that's true, but even with that bug, floats are still displayed in 64 bit mode.
7. Example of a Register value 7843ABCF
Let's focus on the digit 7. A 4-bit binary combination of 0111 created that digit 7. Change that binary combination to let's say 1001 and that digit is now 9 so the word value is now 9843ABCF.
8. The definitions are not technically sound if that makes sense. There's other purposes for the use of OR and AND.
--
"Check if a register holds a 32-Bit value"
I would rename this as this can mean checking if anything is present in the upper 16 bits of a register.
Rename it to something like "Executing a comparison on a register with a value exceeding the 16-bit signed range"
Scruffy's example on discord is right, he just typo'd on the subis instruction.
Btw this actually won't work for your example on the site since your 32 bit value originated from r0. Because if you do something like subis r3, r0, 0xFFFFFFFE, it will just set r3 to 0x00020000 (subis rD, r0, VALUE is lis rD, VALUE). Then the cmplwi r3, 0x5645 instruction won't execute correctly.
You would need to add on a mr instruction to solve this issue. But then at the point you took 3 instructions to do everything, which means lis and ori would have also worked.
Also, don't use r1 for examples unless its for stack related stuff, as r1 is specifically designed to be the stack pointer in PPC.
1.
With Update: Updates the Source Address with new value based on VALUE
Algebraic: I've never once used algebraic labeled instructions believe it or not.
Here's the definition of Load Half Word Algebraic btw (there's other algebraic instructions ofc such as sraw)
The halfword at the Effective Address is loaded in the lower 16 bits of rD. The remaining bits in rD are filled with a copy of the most significant bit of the loaded halfword.
So if the halfword loaded of 0x8000, it will actually load as 0xFFFF8000. Cause the first bit in 0x8000 is 1. Fill every bit of 1 in the upper 16 bits is 0xFFFF.
Negative halfwords in memory take up 32-bits of space (i.e. 0xFFFFFFFD = -3). So what compilers can do to save space in memory is store negative halfwords via sth, so the lower 16 bits are stored to memory only, then the compilers can load these values later with lha to sign-extend them in the register. Example: store the halfword of 0xFFFF8000, will only store 0x8000 to memory, now load it with lha so it loads as 0xFFFF8000. Btw 0xFFFF8000 is -32768 and is the 'lowest' negative number for the 16-bit signed range
Indexed: No use of VALUE, instead another Source Register is used for the Effective Address calculation
2.
Some I know right off the bat...
addi, addis, subi, subis, addic., subic.
Every store/load instruction that is NOT lwm,stwm,lswi,stswi (i havent ever checked lswx, stswx btw). Actually I've never checked the other ones, a generic PowerPC manual I read ages ago claimed that. Btw the Broadway manual (from what ive seen) doesnt have a quick reference/list about instructions and literal 0. There is probably a small paragraph buried somewhere in the manual about it. You could go thru the pain of testing up a bunch of mock instructions with non-zero values in their source registers, and log the results.
3. A quick glance on the file shows its for PowerPC 405. Broadway is based off of PowerPC 750.
4. Its just for example. The point I was making is that the Source Register gets updated with a new value.
5. Whoever told you that is wrong. Compile a not r5, r3 instruction and a nor r5, r3, r3 instruction. It will compile as the same 32-bit code. Go on Dolphin, pause emulation, place in the value of 1 in r3. Execute a not r5, r3 instruction. r5 will equal -2 instead of -1. That's because every bit in a not instruction gets flipped.
Now redo this same example but use neg r5, r3. And r5 will then equal -1, which is obviously the negative value of positive 1.
6. Ye that's true, but even with that bug, floats are still displayed in 64 bit mode.
7. Example of a Register value 7843ABCF
Let's focus on the digit 7. A 4-bit binary combination of 0111 created that digit 7. Change that binary combination to let's say 1001 and that digit is now 9 so the word value is now 9843ABCF.
8. The definitions are not technically sound if that makes sense. There's other purposes for the use of OR and AND.
--
"Check if a register holds a 32-Bit value"
I would rename this as this can mean checking if anything is present in the upper 16 bits of a register.
Rename it to something like "Executing a comparison on a register with a value exceeding the 16-bit signed range"
Scruffy's example on discord is right, he just typo'd on the subis instruction.
Code:
subis r0, r1, 0xFFFFFFFE #Same thing as addis r0, r1, 2; take the upper 16 bits of your 32 bit value in r1, shift them in the lower 16 bits and then sign extend it, that's the value you will use for the subis instruction. 0xFFFE --> 0xFFFFFFFE
cmplwi r0, 0x5645 #Now check the result of the subis instruction with the lower 16 bits of your 32 bit valueBtw this actually won't work for your example on the site since your 32 bit value originated from r0. Because if you do something like subis r3, r0, 0xFFFFFFFE, it will just set r3 to 0x00020000 (subis rD, r0, VALUE is lis rD, VALUE). Then the cmplwi r3, 0x5645 instruction won't execute correctly.
You would need to add on a mr instruction to solve this issue. But then at the point you took 3 instructions to do everything, which means lis and ori would have also worked.
Also, don't use r1 for examples unless its for stack related stuff, as r1 is specifically designed to be the stack pointer in PPC.