PowerPC Page Tables Tutorial

[Gaberboo]

Permission related bits are also present and will override the PP bits in a PTE

Not quite, these bits change the meaning of the PP bits, the key in the SR being set results in two PP bit combinations (00 no access, 01 read only) being reduced access, and not being set causes both these combinations to be read/write. PP bit combo 11 is always read only and 10 is always read/write

bit 0 = Must be 0 or else the SR will be used for an I/O device

Broadway doesn't support direct store segments and so simply triggers a DSI for any access in a segment with an SR that has this bit set and doesn't translate with a BAT. 

Bits 7 thru 15 within HTABORG is known as the "Maskable Bits". Meaning however many zeroes were required is the amount of high/one bits are required to be set in HTABMASK.

Broadway's response to not following this is to just OR HTABORG with the hash anyway, according to a comment in Dolphin's source code. (Note I do not encourage doing this.)

Page Tables cannot cover less than 8MB or more than 4Gbyte of memory.

The values are a recommendation based on physical memory, on the expectation at least some physical memory will be used in multiple pages (say if an operating system is providing a file to multiple programs) and/or the page table gets PTEs clumped in one spot (Which can be somewhat remedied with smart setting of VSID). Doing some math says the absolute limit of a 64 KiB page table is mapping 32 MiB worth of pages, but pushing the limits like this poses problems similar to when your computer disc space is full.

Please NOTE that you could use a double-float store mechanism or the dcbz instruction to clear the page table

Integer stores are going to be faster than storing doubles if you only write the first word of every PTE to zero and I am willing it bet it's faster even if you write 0s to the entire table, since it's likely IBM optimized those more. I'll try to set up a timing comparison on console for this sometime.

construct_pte:
stw r0, 0 (r11)
stw r7, 0x4 (r11)

This is only ok if the page table isn't in use, a PTE should only be valid if it's ok for the processor to see it, with either address translation on this requires the order to be swapped, an eieio placed between the two instructions to prevent out-of-order shenanigans, and a following sync so the processor waits for the PTE to be written before proceeding.

Sidenote, a PR for mkw-sp I coauthored featured usage of page tables https://github.com/stblr/mkw-sp/pull/495 (I wrote the original page table code, it looks a lot nicer than when I first wrote it)