Chapter 12: Index Type and Update Type Loads/Stores
Back in Chapter 10, you've learned about the most basic load and store instructions. A typical load or store instruction would involve an Effect Address being calculated using the following formula...
rA + SIMM = Effective Address
Well for Index type Loads/stores, there is no SIMM. You have two source registers (rA and rB). Therefore the Effective Address is calculated in the following manner...
rA + rB = Effective Address
For example, lets dive into the Load Word Zero Indexed (lwzx) instruction.
Load Word Zero Indexed:
lwzx rD, rA, rB #rA + rB = Effective Address (EA). Load word located at EA into rD
Let's say we have the following instruction....
lwzx r0, r11, r10
with...
r11 = 0xFFFFFFFD
r10 = 0x4080019D
First calculate the EA..
0xFFFFFFFD + 0x4080019D = 0x4080019A
0x4080019A is the EA. Therefore whatever word value located at 0x4080019A will be copy-pasted from memory into r0. Whatever was in r0 beforehand, is now completely overwritten.
Here's a pic of right before the instruction is going to execute. r11 is outlined in red. r10 is outlined in blue. The word in memory that will be loaded is outlined in green.
Now we execute the instruction. Let's take a look...
We see (via the green outlines and arrow) that the word value 0x025B0000 has been copy-pasted into r0.
For halfwords you can use lhzx (syntax: lhzx rD, rA, rB). Just like with lhz, any halfword that is loaded into a register, is always loaded as 0x0000XXXX, with XXXX being the loaded halfword.
For bytes, you can use lbzx (syntax: lbzx rD, rA, rB). just like with lbz, any byte that is loaded into a register, is always loaded as 0x000000XX, with XX being the loaded byte.
Now let's go over Indexed-Type Store Instructions.
Store Word Indexed:
stwx rD, rA, rB
This is simply the opposite of lwzx. EA is calculated via rA + rB. The word (entire value) of rD is copy pasted to the EA.
Store Halfword Indexed:
sthx rD, rA, rB
EA = rA + rB. Lower 16-bits of rD are copy-pasted to EA.
Store Byte Indexed:
stbx rD, rA, rB
EA = rA + rB. Lower 8-bits of rD are copy-pasted to EA.
Okay so the Index-Type Loads/Stores are simple enough. Let's dive into some more complex loads & stores. These are the Update-Type load and stores.
Load Word Zero then Update:
lwzu rD, SIMM (rA)
So similar to a plain-jane lwz instruction, we calculate the EA using SIMM + rA. Once the EA has been calculated, the word value at the EA is loaded into rD. Now here's the kicker, *AFTER* the word value has been loaded into rD, rA's value gets replaced with the calculated EA. Confused? Let's review it in 3 simple steps...
Example lwzu instruction!
lwzu r0, 0x0024 (r4)
If we were to use a regular lwz instruction instead, we would need 2 instructions total. The lwz then an addi.
lwz r0, 0x0024 (r4) addi r4, r4, 0x0024
Let's pretend r4 = 0x40800180. Here's what occurs in the above code snippet.
Instead of doing a lwz + addi, we can use a single lzwu instruction
lwzu r0, 0x0024 (r4)
This is the exact same thing as the lwz+addi code snippet. Let's go over this lwzu instruction using the provided example values via some pictures. Here's a pic of right before the lwzu gets executed....
The source register is outlined in red. The word located in memory, that will be loaded, is outlined in green. Let's execute the lwzu now....
As you can see, the green outlined word gets loaded into r0. The source register (outlined in red) now contains a new value of 0x408001A4.
Store Word then Update:
stwu rD, SIMM (rA)
This is just the opposite of lwzu. The EA is rA + SIMM. The word value of rD is stored at the EA. *AFTER* the store has occurred, rA's value is now the EA.
Example:
stwu r5, -0x4 (r31)
Let's say...
r31 = 0x8055699C
r5 = 0xFFFFFFFF
What occurs~